1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a circuit for use in a semiconductor memory device for controlling the pre-charging time of the bit lines of an array of memory cells for storing data therein.
2. Description of the Background Art
As an electrically programmable non-volatile memory, there has so far been known a type of non-volatile memory including an array of memory cells, each of which is composed of transistors and interconnected to a word line and a bit line to generally form a bi-dimensional matrix, in which the bit line of any of the memory cells to be read out is connected via a selector to a read-out amplifier to cause the memory cell to conduct current, which is in turn compared to the current of a reference memory cell so as to read out data stored in the cell.
In this type of non-volatile memory cell, when the readout operation is to be switched from one memory cell to another, the control bit line is connected to the memory cells at all times in the same direction, thereby causing no significant change in current flowing over the control bit line. However, a memory cell to be read out includes the possibility of a read “1” cell, from which to read out binary “1”, and a read “0” cell, from which to read binary out “0”. Hence, if a bit “1” is read out followed by reading out a bit “0”, for example, then the current continues to flow until the bit line is charged to a certain level, thus causing it to take some period of time until determining a binary “0” read out.
With such a readout system of non-volatile memories, it would be possible to speed up the readout of bit “0” by using a CSV (memory cell readout voltage) level as a reference voltage for a readout amplifier, i.e. amplifier reference voltage, setting the voltage on the bit line in a stabilized state to a voltage approximately equal to the voltage CSV, generating an address transition detection (ATD) signal at the time of switching the cell to be read out, i.e. readout cell, and forcing the bit line, connected to the readout cell thus selected in response to the ATD signal, to be charged to the CSV level, or amplifier reference voltage.
The circuit for generating the ATD signal is provided in a non-volatile memory fabricated in the form of semiconductor integrated circuit device, and is constituted by P-channel metal-oxide semiconductor (MOS) transistors for delay and complimentary MOS (CMOS) transistors for delay so as to be substantially free from voltage and temperature dependency and not susceptible to variations in threshold voltage of the transistors. Such a delay circuit for regulating a delay time against variations in MOS transistor characteristics and ambient temperature is taught by U.S. Pat. No. 5,453,709 to Tanimoto et al., for instance.
With this known technique, however, the delay circuit could not reflect, on its output, variations in cell current and CSV voltage ascribable to the internal voltages, such as voltage CSV charging the bit lines and the voltage cell word line (VCW) voltage. Hence, it is highly probable that the readout of bit “0” could not be sufficiently speeded up although so intended, and delay is caused in the readout of bit “1”.
Specifically, in order to pre-charge a bit line for speeding up the readout of bit “0”, a shorter period of time may be sufficient when the voltage CSV is low because the charging level is low, thus reaching the pre-charging state in such a short time. Conversely, when the pre-charging period is prolonged, the bit line is over-charged, thus causing the readout of bit “1” to delay.
The period of time to pre-charge a bit line to speed up the readout of bit “0” is needed longer when the voltage CSV is high because the charging level is high. If the pre-charging time is short, the charging is insufficient, thus causing the readout of bit “0” to delay.
In case the voltage VCW is low in level, the current flowing through a memory cell, that is cell current, is decreased to cause the charging time to be prolonged, thus causing delay in readout of an expected “1”. It is therefore necessary to make the charging time shorter. Since the cell current in this case is inherently small., the readout of an expected “0” may be accomplished quickly even with a short charging time.
In case the voltage VCW is of a low level, the cell current is increased. Thus, if the charging time is prolonged, to a more or less extent, the charges stored on a bit line are restored quickly through the memory cell to its optimum level. Hence, the delay is scarcely caused in the readout of an expected value of “1”. Conversely, for readout of an expected value of “0”, leakage may occur in a memory cell where the write of the bit is insufficient to render it difficult to read out the binary “0”. It is therefore necessary to charge the bit line sufficiently. If the charging time is shorter in this case, the delay may be caused in reading out an expected value of “0”.